1. Field of the Invention
The present invention relates to semiconductor wafer manufacturing. More particularly, the present invention relates to a wafer for preventing the formation of silicon nodules, the manufacturing of wafers for preventing the formation of silicon nodules. Still more particularly, the present invention relates to epitaxy and a method for producing an epitaxial layer on a wafer with superior dopant uniformity and a nodule-free, smooth underside.
2. Description of Related Art
In semiconductor device manufacturing the structure of a lightly doped layer on a heavily doped substrate or wafer is commonly required. This structure provides electrical benefits for designers of integrated logic circuits such as transistor latch-up suppression, and soft-error immunity. In addition, numerous discrete power transistors and diodes are built using this structure type. Epitaxial wafers have been a prime method used in the semiconductor industry for the formation of lightly doped semiconductor layers on heavily doped semiconductor substrates or wafers. Epitaxial wafers also can have the advantage of providing a surface free of defects that can be grown into the substrate during the crystal formation process.
The epitaxial growth process for an ideal case is described below as depicted in FIG. 1. As mentioned above, epitaxy involves the deposition of a thin layer of semiconductor material, e.g., silicon, onto the surface of a single crystal semiconductor wafer while maintaining the same crystallographic orientation inherent in the wafer substrate. An epitaxial deposition process which is commonly used in the semiconductor industry is referred to as chemical vapor deposition (CVD), i.e., the growing of an epitaxial layer on a substrate from a gas.
Epitaxial deposition occurs in chamber 150 of an epitaxial reactor. This process is a high temperature process in which silicon source gases are reacted on the surface of a wafer to grow epitaxial silicon crystal. Wafer 100 rests on susceptor 160 during epitaxy. In a typical configuration, susceptor 160 may incorporate one or more wafer pockets 162 which are approximately as deep as half of the thickness of wafer 100 and is slightly larger in diameter than wafer 100. Wafer 100 and susceptor 160 is heated to temperatures ranging from 1000 deg. C. to 1200 deg. Celsius (° C.) for the process using infrared lamps or radio frequency power sources. During the CVD process silicon source gas molecules 120 can diffuse around the periphery of wafer 100 and between wafer 100 and susceptor 160. Typical silicon source gases are trichlorosilane and dichlorosilane (depicted in the figure as SiH2Cl2 120). Hydrogen is the carrier gas (H2 122) used to transport the other chemical reactants to deposition chamber 150. The reaction in epitaxial chamber 150 is depicted below.

Silicon source gas 120 and dopant gas (not shown) may be also blended with hydrogen carrier gas 122 and injected into chamber 150. An exemplary P type dopant source gas is diborane and N type gas dopant sources are arsene or phosphene. Concentration of these dopants and layer thickness are controlled to produce very uniform electrical characteristics of epitaxial layer 110.
The CVD process described above has significant drawbacks when applied to epitaxy as will be explained below. A crystal substrate is manufactured by pulling crystal ingots from molten semiconductor material. The melt from which the ingot is pulled is doped with atoms in order to change the electrical characteristics of the material (e.g., the ingot may be doped with boron which acts as acceptors, or conversely the substrate may be doped with arsenic, phosphorus or antimony which acts as donors). The ingot is then divided into individual wafers by sawing, etching and polishing the semiconductor substrate into the desired shape and thickness. Silicon substrates used for epitaxial deposition often have a silicon oxide layer on the backside to prevent the dopant atoms in the substrate from out-gassing during the high temperature epitaxial process, as shown in FIG. 2A.
In the course of CVD, as the epitaxial growth process progresses, the wafer substrate and susceptor are heated at a high temperature in the hydrogen atmosphere of reactor chamber as discussed above. As the primary surface and periphery of the wafer is accepting the epitaxial layer, dopants in the wafer are often discharged into the high temperature vapor of the chamber from the underside or secondary surface of the wafer. The out-gassed dopants in the chamber are trapped within the vapor phase growing the epitaxial layer. These out-gassed dopants result in an “auto-doping” phenomenon and as a consequence, the concentration of dopants in the epitaxial layer becomes non-uniform. If uncontrolled, substrate out-gassing will produce poor resistivity uniformity in the epitaxial layer.
The prior art solution to the out-gassing problem is a layer of protection film applied to the secondary surface of a wafer prior to epitaxy as depicted in FIGS. 2A-2D. Protection layer film 220 is typically comprised of one of silicon dioxide and silicon nitride or the like. These protection layers are commonly deposited in a thermal furnace or deposition reactor, however, those of ordinary skill in the art will recognized other formation means including growing an oxide protection layer by thermal oxidation. Protection layer 220 is typically between 3000 to 10,000 angstroms (Å) in thickness.
Protection layer 220 performs two primary functions: the protection film on the secondary surface of wafer 100 prevents dopant atoms in substrate 100 from out-gassing during the high temperature epitaxy process; and also the protection layer protects substrate 100 from being etched by the high temperature gasses in chamber 150. Without the protection layer on the secondary surface of the wafer, the gaseous hydrogen and deposition byproducts (HCl, Cl2) in the chamber will etch away the substrate adjacent to susceptor 160, thereby releasing even more dopant into chamber 150. Optionally, protection layer 220 can be extended to cover the periphery of wafer 100 in order to seal more surface area of the substrate.
Sealing the wafer dopant atoms in the wafer is necessary to prevent the out-gassing dopant atoms from being incorporated into the growing epitaxial layer. If uncontrolled, the substrate dopants released into the chamber from out-gassing will auto-dope the epitaxial layer and generally result in poor resistivity uniformity in the epitaxial layer.
However, when forming epitaxial layer 110 on substrate 100, the silicon source gas molecules present in the CVD epitaxy process preferentially deposit on silicon surfaces over silicon oxide or nitride surfaces of protection layer 220. This preferential deposition is due to a reluctance of the silicon source gas molecules to seed on the silicon oxide or nitride surfaces. No initial seed deposition will take place on the silicon oxide or nitride until sufficient gas density is present and sufficient nucleation time has passed. This preferential deposition 220 will cause nodules to form 232 due to pin holes or porosity in protection layer 220 which expose the underlying silicon of substrate 100 and which then acts as a seed site for nodule growth. These needle-like silicon projects, shown in spur projection 222 in FIG. 2C, occur when the source gas enters a pore or pinhole in protection layer 220, causing the silicon to grow abnormally into a needle shaped projection through the protection layer and onto susceptor 160. Another, more common result is the formation of nodules 232 that are attracted by islands of silicon deposition that seed on protection layer 220. These islands of silicon then attract more silicon deposition resulting in nodule formation. Similarly, the formation of spur projection 222 also attract or seed nodule growth. The fugitive gases which lead to the formation of the nodules and spur projections come from the source gases that are injected into the epitaxial reactor for the deposition of the epitaxial layer. A second source for the fugitive gases is the etching of silicon that has deposited on the susceptor prior to or during the epitaxy process. Silicon that has deposited on the susceptor is etched away into the vapor phase by deposition gases and byproducts (Hydrogen, HCl, Cl2). These gaseous silicon molecules then act as a source gas for the formation of nodules on the protection layer.
The formation of silicon nodules 232 result in a non-uniform secondary surface that cause particulate problems, abrasion of wafer carriers, poor focus in photolithography processes and the inability to obtain good vacuum on a wafer vacuum-chuck. Spur projections 222 and silicon nodules 232 are prone to separate from the substrate during transfer and handling of the wafer, thereby contribute to generation of unwanted particulate matter. Additionally, during epitaxy the preferential deposition of the source gas on the substrate material over the protection layer material can increase the occurrence epitaxial crowns 234, which are extraordinary growths of epitaxial silicon at the junction of epitaxial layer 110 and protection layer 220.
The occurrence of nodules require an extra polishing step, if permissible, subsequent to the epitaxial deposition. Prior art methods for controlling nodule formation during epitaxy required a tradeoff in the severity of the nodules and the effectiveness of the dopant protection layer. One approach is to remove the protection layer near the edge of the wafer to expose the wafer. This portion of the exposed wafer then acts as a seed layer for silicon to deposit on, but as a smooth film layer rather than uneven nodules. This approach has the disadvantage of exposing the wafer (i.e., the seed layer) to the epitaxial chamber which out-gasses dopant during the high temperature epitaxy process and auto-doping the epitaxial layer, thereby impairing epitaxial resistivity uniformity.
Another approach is to modify the design of the susceptor pocket 162 with the goal of reducing the amount of fugitive gases that diffuse to the secondary surface of the wafer. In addition the pocket can be modified to reduce the amount of contact between the susceptor and wafer and/or increase the distance between portions of the wafer and the susceptor. Pocket designs that are used to accomplish these goals include providing a step near the pocket edge or forming the pocket with a dish or conical shape. These pocket modifications have the disadvantage of decreasing the thermal coupling of the wafer to the susceptor which can create non-uniform temperature profiles across the wafer which adversely affect the epitaxy process